As a popular machine learning (ML) model, deep neural networks (DNNs) continue to inspire new development of on-chip intelligence for wide range of emerging applications including vision, unmanned vehicle, consumer electronics, and the IoT devices, due to their non-linear characteristics, and self adaptive features. DNNs techniques, however, require enormous computational power, which is not always available on embedded systems due to their serve resource constraints. "For instance, popular DNNs such as VGGNet and ResNet, contain over 140 million floating-point (FP) parameters and performs over 15 billion FP operations to classify one image".
Customized and reconfigurable hardware such as ASICs and FPGAs can offer significant improvements in energy efficiency and power dissipation while speeding up computations, and providing high performance computing (HPC) at minimal cost power consumption.
The goal of this tutorial is to present circuit and system designers current efforts of on-chip intelligence, and identify open problems in designing future ultra-low power hardware. To promote easy and effective engagement in the field, the tutorial will deliver an introduction to DNNs, motivation for energy efficient memory design, Examples of state-of-the-art architectures, and frameworks (tookits) that are widely used for ML synthesis.