6: Neuromorphic Computing: Devices, Circuits and Algorithms
- Vishal Saxena, University of Idaho
There is a growing need for entirely new paradigms of computing that “can proactively interpret and learn from data, solve unfamiliar problems using what it has learned, and operate with the energy-efficiency of the human brain.” In alignment with this goal, large-scale integration of CMOS mixed-signal integrated circuits and nanoscale emerging devices, such as the phase-change (PCRAM) and resistive RAM (RRAM), etc., can enable a new generation of Neuromorphic computers that can be applied to a wide range of machine learning problems. This tutorial combines an overview of recent advances in energy-efficient Neuromorphic Computing Circuits and Systems for embedded deep learning applications. The tutorial aims to provide a complete picture to the audience; from emerging devices, to transistor-level neural circuit design, and learning algorithms to put the system together. Case studies will be presented for Neuromorphic System-on-a-chip (NeuSoC) with applications to spike-based machine learning followed by recent advances in the area spiking neural networks and neuromorphic hardware.
Vishal Saxena is Micron Endowed Professor in Microelectronics and Associate Professor of Electrical and Computer Engineering at the University of Idaho. He obtained his B. Tech. degree in Electrical Engineering from Indian Institute of Technology, Madras in 2002. Subsequently, he graduated with a Ph.D. from Boise State University, ID in 2010 in the area of wideband Delta-Sigma ADC design. In between, he has held senior design position in broadband communication system design in a start-up, circuit design positions in Micron Imaging group (later Aptina) in Boise, ID and Lightwire Inc. in Allentown, PA. At University of Idaho, he directs the Analog Mixed-Signal and Photonic Integrated Circuits (AMPIC) Lab and teaches courses on Analog, Mixed-Signal, and RF IC design. Dr. Saxena received the prestigious 2015 NSF CAREER, and 2016 AFOSR Young Investigator Program (YIP) awards. He was also recognized as 2016 Idaho’s accomplished under 40. He is a member of IEEE and has been an Associate Editor for IEEE TCAS-II journal. He currently serves on the steering committee of IEEE MWSCAS conference. His research interests include CMOS photonic interconnects, RF/mmWave photonics, data converters, Neuromorphic circuits and systems, and novel circuits for machine learning.