Abstract:

Conventional and now Post-Dennard’s scaling of integrated circuit technology is becoming more and more difficult, challenging and costly. Even foremost semiconductor industry leaders start admitting that 7nm node might be the final technology node that will go to production due to fabrication and design challenges, and astronomical development cost.

3D technologies differ greatly in fabrication, advantages, design and test challenges, and their targeted applications. There is a significant demand for EDA tools that can efficiently and creatively explore design spaces and stimulate new paradigms for designers to take full advantage of these technologies. Many issues and challenges must be overcome before true 3D integration technologies can bear fruit. Can we do it and at what cost? Will 3D integration deliver on the promises?

The need to expand ICs into the third dimension originates with the increasing contribution of long interconnects to most performance parameters in complex electronic systems: energy efficiency, bandwidth, yield, and reliability. 3D integration is a promising solution to meet the challenge of rising system requirements: better performance, increased functionality, lower power consumption, higher bandwidth, and a smaller footprint. The menu of available 3D integration technologies includes wafer-level packaging (3D WLP), 2.5D Interposer, stacked ICs (3D SICs), full monolithic 3D ICs, and heterogeneous integration; 3D system integration can leverage one or more of these approaches. 3D stacking opens tremendous opportunity for integration of micro/nano/bio systems into one package, as well as allowing for efficient integration of digital, analog, RF, and sensor systems. The industry is also now looking at monolithic 3D to be the future technology driver.

This tutorial presents an overview of technologies currently being developed, modification to design methodologies, and summary of new evaluation and optimization techniques to enable successful designs with acceptable yield and reliability in the presence of process and environmental (temperature and Vdd) parameter variations. We start with an introduction to stacking 3D (and 2.5D) technologies including interposers and TSV challenges, and follow by an overview of various multi-transistor layer options in monolithic 3D ICs. 3D Stacked ICs (3D SIC) are fabricated by stacking IC chips using TSV interconnects. We will discuss various materials and types of TSVs that are considered to be one of the major bottlenecks of this technology followed by wafer aligning, thinning, and bonding, TSV-induced thermo-mechanical stress and its influence on performance of neighboring devices and interconnects will be discussed. Influence of TSVs on performance and dynamic power dissipation of 3D systems will be evaluated by modeling TSV capacitances and resistance. TSV layout solutions and positioning options will be evaluated using optimization techniques.

It will be followed by an overview of fully monolith 3D ICs that are built in layers of active devices on a single semiconductor wafer, which is then diced into 3D ICs. The key challenges of fully monolithic ICs include process temperature limitations due to active transistor layer that is placed on top of another active transistor layer. The path to monolithic 3D requires the development of new transistor types and processes. This new 3D geometrical structure, of active layers with a very limited and very local interconnects, presents new challenges for designing and optimization at logic and physical layout stages. The monolithic 3D IC technology has been researched at various academic institutions and industry including Stanford University’s carbon nanotube, CEA-Leti’s low-temperature sequential 3D IC, and various technologies being developed at MonolithIC 3D. At present, fully monolithic 3D ICs are still a developing technology and are considered by most to be several years away from production. The industry, however, is already looking at monolithic 3D to be the future technology driver.

We will conclude, with presenting challenges and opportunities of 3D technologies seen through the eyes of a 3D layout designer. Performance, power, variability, reliability and yield aspects that can be altered through 3D physical layout design will be emphasized. Early design evaluation using a 3D floorplanning tool will be presented using case studies. Through the tutorial we will show various applications developed so far and future ones.

Biographies

• Malgorzata Chrzanowska-Jeske

  is Professor of Electrical and Computer Engineering and Director of the VLSI & Emerging Technology Design Automation Laboratory at Portland State University. From 2004 to 2010 she was Chair of the ECE department at PSU, which she joined in 1989. Previously, she has served on the faculty of the Technical University of Warsaw, and as a design automation specialist at the Research and Production Center of Semiconductor Devices in Warsaw. She holds M.S. degree in electronics engineering from Politechnika Warszawska (the Technical University of Warsaw) Warsaw, Poland, and the PhD degree in electrical engineering from Auburn University, Auburn, Alabama.

  Her research interests include CAD for VLSI ICs, MS-SOCs, 3D ICs, nanotechnology and nano/bio systems, design for manufacturability and design issues in emerging and renewable technologies. She has presented tutorials, keynote and invited talks at various international conferences and events. She has published more than 150 technical papers and serves as a panelist and reviewer for the National Science Foundation (NSF), and as a reviewer for National Research Council Canada (NRC) and many international journals and conferences. She presented keynote, plenary and tutorial lectures at various international conferences. She received the Best Paper Award from Alabama Section of IEEE for the best IEEE Transaction paper in 1990 and IEEE Council on Electronic Design Automation 2008 Donald O. Pederson Best Paper Award in IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems. Her research has been supported by the NSF and industry.

  Dr. Chrzanowska-Jeske has served in various roles on the Technical, Steering, and Organizing Committees of many international conferences and workshops, and as Senior Editor, Associate Editor and Guest Editor of international journals. Currently, she serves as Associate Editor for Transactions on Circuits and Systems II. She served for two terms on Board of Governors of IEEE Circuits and Systems Society (CASS) where she was also Chair of the Distinguished Lecturer Program and Chair and a founding-member of Women in CAS. She served as Vice President for Technical Activities for the IEEE Nanotechnology Council (NTC), and was just elected to serve as NTC VP for Finance starting January 2019. Currently she serves as chair of Nanoelectronics and Giga-scale Systems Technical Committee of the IEEE Circuits and Systems Society, and recently, she was a Technical Program chair of 2018 NTC Nanotechnology Materials and Devices Conference. She is a Life Senior Member of IEEE.